Call DLL Example (how to) with alternative installation.

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jondr
Posts: 12
Joined: Wed Feb 01, 2006 2:05 pm

Call DLL Example (how to) with alternative installation.

Postby jondr » Tue Feb 14, 2006 5:03 pm

Attached is C code for a DLL that determines the CPU level of a target machine. I include the compiled DLL into my SUPPORTDIR folder on the target machine and use the "Call DLL" plugin to run it and return the resultant value to the script. Included in the comments of the program code is a more complete explanation, as well as a text copy of the pertenant portion of the installation script. It details how to make functions callable, and how to compile and create a DLL using gcc with MinGW (Minimalist Gnu for Windows).

I am not a C coder by practice. The original code was an program written by Gerald Heim at the University of Tübingen, Germany. It is released under GNU General Public License and can be downloaded from:

http://www-ti.informatik.uni-tuebingen. ... puid-1.3.c

from software page:

http://www-ti.informatik.uni-tuebingen. ... /software/

(Thank you, Gerald). Much more can be done with the code than I have used; my focus was narrowed for my own purposes.

File Attached:

tstcpuid.c

http://www.installaware.com/forum/files ... tstcpuid.c

Edited for this note from Gerald Heim (check my code for his fix):
---------------------------------------------
Hello for a 2nd time Jon,

I did it. Integrated your tables to my Linux version as
a quick hacked update.

Please check your version for a missing:
{ 31, "PBE", "Pending Break Enable" },
in Intels features. I think you have 27 instead of 31.

Please also note that the procedure identify_amd
will happily fail on AMD-64 when compiled in 32 Bit mode:

CPUID(AMD - x) Textual processor description is "AMD Athlon(tm) 64 Processor 3500+"
CPUID(AMD - 5) : Data TLB with 32 entries, 255-way set associative
CPUID(AMD - 5) : Instruction TLB with 32 entries, 255-way set associative
CPUID(AMD - 5) : L1 Data Cache is 64k (1 lines per tag, 64-byte lines, 2-way set associative
CPUID(AMD - 5) : L1 Instruction Cache is 64k (1 lines per tag, 64-byte lines, 2-way set associative
CPUID(AMD - 6) : WARNING! This has not been tested!
CPUID(AMD - 6) : L2 Unified Cache is 2k (129 lines per tag, 64-byte lines, 0-way set associative

L1 Cache could be correct, but TLBs sure are larger.
L2 is non-sense :-)

cheers
-gerald

PS: Find it on http://www-ti.informatik.uni-tuebingen. ... /software/
--
Jon

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